Services

Video meeting . 20 mins

Getting Started in Design Verification (VLSI)

Start your VLSI DV journey with clarity
FREE

About me

-Good knowledge of Hardware Descriptive Language(Verilog) and Hardware verification Language(System Verilog), and Universal Verification Methodology -Hands-on experience using Questa sim and Model sim, Xilinx Vivado -Good understanding of UVM RAL -Good knowledge of Protocols of AMBA(APB, AXI)