Getting Started in Design Verification (VLSI)

This is a 1:1 guidance session for students and early-career engineers who want to get started in Design Verification (VLSI).

We’ll discuss your current level, clear common confusion, and define a simple learning path.

You can expect guidance on:

• What to learn (SystemVerilog, UVM basics)

• How to approach projects

• Common mistakes to avoid

• Next steps for building a DV career

The goal is to help you leave with clarity and a practical direction.