Services
Video meeting . 60 mins
Portfolio Mini Project
Verilog Mini Project: Synthesizable RTL + Verification
About me
I’m a Design Verification Engineer with 10+ years delivering production SoCs across automotive, Edge AI, consumer, and low‑power domains. I help freshers and experienced VLSI engineers build portfolio projects, master RTL/UVM/FPGA workflows, and crack semiconductor interviews through hands‑on coaching, mock interviews, and project supervision. Book a free 15‑min audit to get a tailored roadmap and project plan.