Portfolio Mini Project

One‑line promise

Get a portfolio mini project, hands‑on Verilog practice, and interview talking points in four focused sessions.

Who this is for

1. Final‑year students preparing capstone projects or internship applications.
2. Freshers aiming for their first VLSI role or internship.
3. Learners who want a guided, practical introduction to synthesizable RTL and basic verification.

Format and commitment

1. Format: 4 × 60‑minute 1:1 live sessions (screen share) + asynchronous code review and feedback between sessions.
2. Total time: 4 ×1 hours 1:1 session over 2–4 weeks including homework.
3. Communication: Slack/Email for quick questions; GitHub or Google Drive for repo sharing and PR‑style feedback.

Session plan

1. Session 1 — Kickoff and Plan (60 min) Focus: fundamentals checklist, toolchain setup (simulator, lint, synthesis), personalized learning plan, project scoping. Homework: small lab to verify toolchain and coding style.
2. Session 2 — Synthesizable Verilog Lab (60 min) Focus: coding standards, modular RTL patterns, clock/reset handling, linting and synthesis considerations. Homework: implement one module from the mini project.
3. Session 3 — Basic Verification (60 min) Focus: directed tests, simple assertions, testbench structure, waveform debugging, basic coverage ideas. Homework: write directed tests and run regressions; capture waveforms for review.
4. Session 4 — Project Review and Interview Prep (60 min) Focus: code review, integration checks, demo walkthrough, 5 targeted interview Q&A bullets and concise impact statements. Deliverable handover and next‑step recommendations.

Deliverables

1. Mini project Git repo with RTL, testbench, and scripts.
2. One‑page project summary suitable for resume or LinkedIn.
3. 5 interview Q&A bullets to explain design choices and verification approach.
4. Session recordings and written feedback for each session.

Outcomes and success metrics

1. Working synthesizable module that can be synthesized or simulated.
2. Basic verification skills: directed tests, assertions, and waveform debugging.
3. Portfolio artifact ready to show in interviews or include in applications.
4. Confidence to explain design decisions and verification steps in interviews.

Prerequisites

1. Basic digital logic understanding.
2. Introductory Verilog familiarity.
3. Access to a simulator (modelsim/iverilog/questa) and a code repo (GitHub/Drive).