👋 Hi, I’m Rahul Teradal Design Verification Engineer | GATE Qualified | SystemVerilog & UVM Mentor I’m a GATE-qualified Design Verification Engineer with hands-on industry experience in SystemVerilog, UVM, and SoC/IP-level verification. I currently work as a Design Verification Trainee at Sion Semiconductors, where I actively contribute to building reusable UVM environments, developing assertion-based verification, executing constrained-random testing, and achieving functional and code coverage closure using tools like QuestaSim and Cadence Xcelium. My practical experience spans multiple real-world verification projects including AXI VIP development, AHB–APB bridge verification, multi-port SRAM verification, and synchronous FIFO verification. Through these projects, I’ve gained strong expertise in protocol-level verification, testbench architecture, SVA, coverage-driven verification, and RTL debugging at both IP and SoC levels. I strongly believe that Design Verification becomes intuitive when concepts are explained step by step with real examples, rather than just theory. Through 1-to-1 doubt clearing and mentoring sessions, I help students and early-career engineers understand: SystemVerilog & UVM from fundamentals to advanced topics Testbench components (driver, monitor, scoreboard, coverage) Assertions (SVA) and protocol checks AXI / AHB / APB protocols Debugging simulation and RTL issues Project guidance and interview preparation for DV roles I have also published 7 research papers (4 IEEE) and achieved AIR 1889 in GATE 2024 (ECE), which helps me guide aspirants both academically and industry-wise. 📌 If you’re aiming to build a strong foundation or transition into ASIC/SoC Design Verification, I’d be happy to guide you through personalized 1-to-1 sessions.