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VLSI Verification Projects

Package

3Products

1 x AHB-to-APB Bridge Verification using SV & UVM

This project focuses on the complete verification of an AHB-to-APB bridge using SystemVerilog and UVM methodology, follo… Read more

1 x DV Project-AXI VIP Development using SV & UVM

This project demonstrates the complete development of an AXI4 Verification IP (VIP) using SystemVerilog and UVM methodol… Read more

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This bundle provides complete, industry-oriented verification projects based on AMBA protocols using SystemVerilog and UVM methodology.

The projects are designed to reflect real ASIC design verification workflows and are highly suitable for interview preparation and hands-on learning.

Projects Included:

• AXI4 Verification IP Development using SystemVerilog & UVM

• AHB-to-APB Bridge Verification using SystemVerilog & UVM

Key Highlights:

• UVM-based reusable verification environments

• Protocol-compliant stimulus and monitoring

• Assertion-based protocol checking (SVA)

• Functional coverage and scoreboards

• Ready-to-run simulation setups

• Interview-focused project structure

• Clean, modular, and scalable codebase

This bundle is ideal for VLSI students, ASIC verification aspirants, and professionals preparing for design verification roles involving AMBA protocols.

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₹1,499₹2,498

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VLSI Verification Projects

Rahul Teradal