17 years hands on experience in ASIC/FPGA/SoC Verification. Currently working on IP , Sub-System, SoC level Verification & Post Si validation of HBM3 & GDDR6 Memory controller Subsystem for a Graphics SoC meant for Super Compute applications. Previously worked on Fabric Sub System , MIPI DSI IP(C-PHY & D-PHY), Boot and Power management Sub System, Always-on Sub Systems. Developed SV, UVM & C++ based verification environment from scratch. Involved in the complete life cycle of IP & SoC Level Verification and Validation. Expertise in both Pre & Post Si Validation. Skilled in verification methodologies like SV/UVM etc. Have multiple awards , paper selections at various conferences(details below) Won Best paper award in DAC 2020 in 'Designer Track Front-End' for the following paper:- 1) 'Achieve Better Communication In Your UVM TB Using These Obscure UVM Classes'(Main author/speaker) Have following 2 paper selections at DVCON India 2019:- 1) 'Using Software Design Patterns in Test Bench Development for a Multi-Layer Protocol' (Main author/speaker) 2) 'Adaptive UVM <-> AMOD(C++ based algo. model) testbench for configurable DSI IP' (Co-Author) Have 1 paper selection at DAC 2021:- 1) Get more out of your UVM register layer!