Leet Code for VLSI - Day 7 (Question & Solution)

LeetCode for VLSI – Challenge 7

Design a parameterized PWM (Pulse Width Modulation) generator in synthesizable Verilog.

1. Requirements:
2. Parameterize the counter width
3. Support synchronous reset.
4. Include an enable signal.
5. Generate a PWM output based on a programmable duty-cycle value.
6. Duty cycle should be adjustable.
7. PWM output should remain LOW when disabled.
8. Use synthesizable Verilog only.