Leet Code for VLSI - Day 6 (Question & Solution)

LeetCode for VLSI – Challenge 6

Design a parameterized synchronous FIFO in synthesizable Verilog.

Requirements:

1. Parameterize the FIFO data width.
2. Parameterize the FIFO depth.
3. Support synchronous reset.
4. Include write_en and read_en signals.
5. Provide full and empty status signals.
6. Do not allow writing when FIFO is full.
7. Do not allow reading when FIFO is empty.
8. Maintain correct ordering of data: first written, first read.
9. Use synthesizable Verilog.