Leet Code for VLSI - Day 4 (Question & Solution)

Leetcode for VLSI – Challenge 4

Design a Pulse Synchronizer to safely transfer a single-cycle pulse from one clock domain to another.

Requirements

1. Input and output clocks are asynchronous.
2. Every input pulse must generate exactly one output pulse.
3. No pulse should be missed or duplicated.
4. Use synthesizable Verilog only.