Leet Code for VLSI - Day 3 (Question & Solution)

Leetcode for VLSI – Challenge 3

Design a parameterized Fixed Priority Arbiter in Verilog.

Requirements

1. Parameterize the number of request inputs (N).
2. The requester with the highest priority should always receive the grant.
3. Only one grant should be asserted at any given time.
4. If multiple requests are asserted simultaneously, grant the request with the highest priority.
5. If no requests are asserted, all grant outputs should remain deasserted.
6. The design should be fully synthesizable.
7. Optimize the design for scalability and minimum combinational logic.