Services
Video meeting . 30 mins
Design Verification Mentorship
Career in design verification
About me
Specialties:
- SV/UVM testbench development
- VIP components driver, monitor, scoreboard development.
- SV/C/ASM based stimulus development
- Creating verification and coverage plan
- RTL & GLS Simulations debug
- Scripting using PERL
- Integration verification of Caches/TCMs/SRAMs in SoC
-regressions triage.
-Knowledge of SoC bootup flow and SoC test flow.
Protocol exposure:
- AMBA APB, AHB LITE, AXI, AXI Stream, NVMe (beginner)
- CAN, LIN, SPI
- RoCE V2 (RDMA)
Scripting language:
- PERL, shell
UNIX utilities:
- Sed, makefile
Tool exposure:
- Cadence xcelium
- Synopsys DVE, Verdi
- QuestaSim
- Vivek is deeply knowledgeable in top-level verification and the RIS engine, impressing with his calm demeanor under pressure. He effectively guides the team, resolves complex issues with precision, and sets high standards with his work ethic. An invaluable teammate, he consistently shares knowledge and leads with clarity.AI-generated from recommendations on
