Currently Pursuing Master's in Electrical Engineer and will be graduating in December 2023. With demonstrated history of working in the field of Design Verification, Computer Architecture through coursework projects, I have spent the last one years honing and learning various technological skills. I have learnt and worked on various Design Verification languages like Verilog ,SystemVerilog and UVM in my ongoing grad studies, in addition to C/C++ which was a part of my undergrad coursework. I have working knowledge of Python & Perl. I'm a Currently Pursuing my Masters from San Jose State University with a major in Design Verification and Computer Architecture. My key strengths are Verilog/SystemVerilog for Design Verification, scripting in Python, an undying thirst for knowledge and an eye of the tiger when it comes to problem solving. HDL: Proficient in Verilog, SystemVerilog, SV OOP, UVM. Working knowledge of SVA, CRT, Python Programming and Scripting: C, Python, C ++, perl Tools: VCS,Xilinx Vivado, keil, MATLAB(basic) Memories: Working knowledge of DDR memories, Multilevel cache system, Virtual memory OS: Comfortable with Windows, Linux and UBUNTU FPGA : DE10 Lite , Nexys A7, Arduino , Jetson TX1 Part-time: Trekker , Chess , Swimmer!