Physical Design Engineer with 5+ years of Experience in RTL2GDSII, Layout and Mixed Signal Designs at block & full chip design. Successfully contributed to the tapeout of multiple chips. Expertise: Synthesis, Floor Planning, Placement, CTS, Congestion analysis, Routing, Static Timing Analysis and Closure, LEC, IR-Drop, EM and SI Analysis, Physical Verification (DRC/LVS/ERC) and Low power analysis. EDA Tools: Synthesis: DC Compiler, Fusion Compiler. Layout: ICC, ICC2, Fusion Compiler. Timing: Prime Time. Equivalence: FM, VCLP. Extraction: Star RC. Physical Verification: Redhawk, ICV, ICC2. Scripting: TCL, Perl, Shell, Linux.