I am an experienced Semiconductor Professional with experience in analog design and Ph.D. in VLSI from VIT Vellore. As an accomplished Analog Design Engineer, I bring a wealth of expertise from my 7+ year tenure in the Research and Semicon Industry. Throughout my career, I have demonstrated history of working on industry standards projects. I have demonstrated a strong track record of successfully managing various challenges, while consistently delivering innovative ideas that have resulted in many International Publications. PROFESSIONAL EXPERIENCE: - ~6+ years of relevant experience in Mixed Signal circuit design in various components for DDR, PLLs, Data Converters etc. - ~3 yrs of expertise in verilog language while carrying various projects in it. - Good exposure to DFT based concepts, including scan chain, ATPG, BIST. - Design experience in most of the following SerDes circuit blocks: Driver; Transmitter; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; and Voltage Regulators. - Design and Post silicon experience in latest cutting-edge processes (10 & 7nm). - Exposure to Cross-Site and cross-Domain team during the different stages of product cycle. - Involved in the process of generating, verifying, and handing off collateral from Custom Building Block (CBB) to Structured Design (SD). This involved collateral generation for circuit blocks as required by the chip integration flow (RV, LEF, XFIRE, PERC, Calibre, hipallf, Review GUI - finale and other supporting views. - My simulation expertise includes functionality and performance simulations, ERC simulations, and reliability simulations covering Gradual Aging, EOS., ELF, RV. - Good understanding of device physics, layout effects, sub-micron effects and device reliability.