I am an experienced VLSI Engineer with a strong passion for designing and optimizing cutting-edge integrated circuits. Proficient in ASIC and FPGA design methodologies, with a track record of delivering high-performance solutions. Skilled in RTL coding, synthesis, verification, and timing closure. I am committed to keeping abreast of market developments and always developing my skills to spur innovation. I am open to collaborating on challenging projects and contribute to the advancement of semiconductor technology. Areas of competence: Digital circuit design (RTL) Static timing analysis Functional and code coverage verification