* Expert in SoC/ASIC DFT architecture, with a proven track record of leading over 18 projects from start to successful tape-out. * Proficient in a wide range of DFT methodologies, including Scan, Compression, OCC, JTAG, Boundary Scan, LBIST, and MBIST. * Skilled in using industry-standard EDA tools such as Synopsys (TestMAX, DFT Compiler, VCS, Formality), Mentor (Tessent, Questa), and Cadence (NCsim, Xcelium). * Experienced in complex hierarchical DFT insertion, pattern generation/retargeting, and formal verification (LEC) for DFT and ECO flows. * Recognized contributor to the field with 7 publications and 2 patents in DFT.