As a Senior Lead Engineer at NXP Semiconductors, I contribute to advancing co-design methodologies that seamlessly integrate die and package design workflows. My role involves creating custom Cadence-SKILL-based solutions to address gaps in existing tool flows, enabling efficient collaboration between design teams. With over nine years of experience in VLSI design and EDA tool development, I bring a strong focus on problem-solving and innovation to every project. My previous tenure at Cadence Design Systems allowed me to lead efforts across cutting-edge technologies, including 3nm and 5nm nodes, RF design flows, and electromagnetic solvers. This experience has honed my expertise in Virtuoso RF solutions and physical verification tools while fostering a results-driven approach to complex challenges. My mission is to empower teams with cutting-edge EDA methodologies, supporting the design of next-generation semiconductor solutions.