I specialize in driving methodology and tool development initiatives for ASIC verification within the Tegra Memory SubSystem (MSS) team. My focus is on optimizing the functional verification flow from a methodology perspective, including simulation, coverage analysis, and more. Leveraging Python and ML, I design and implement tools to enhance efficiency and elevate verification standards. Previously at IBM Systems Labs, I led the global development of an in-house Functional Verification Framework (similar to UVM) in C++, streamlining validation for IBM PowerPC and Z mainframe chips. My contributions included optimizing tool performance, reducing memory usage, and enabling verification engineers to achieve higher functional coverage. Additionally, I played a key role in developing a DevOps-driven CI/CD test regression suite using Python, Jenkins, Grafana, and MongoDB. Beyond verification, I am an active inventor with 13+ US patents spanning hardware memory characterization, XR (AR/VR), HMI, biosensors, smart fabric, and robotics. My Master's research extended into quantum computing, leading to collaborations with the IBM Quantum Group and publications in conferences such as VLSID and DVCon US.