Handled Block/Full Chip/SOC level PnR,STA and Signoff activities. Across various technology Nodes(5nm,7nm,10nm,14nm,16nm,28nm). Currently Working in Intel India as Deep Learning Hardware Engineer. ● 7 Years of Experience in Cluster and Block execution using Innovus/ICC2 across various technology nodes. ● Have Experience in End to End Full chip cluster and block execution (RTL2GDSII), Including FC cluster as well as block level timing (PT, Tweaker) , IR (ANSYS Redhawk) , FV (Formality, Conformal) and PV (ICV , Calibre) closure for the handled Cluster and its blocks. ● Block and Cluster level SDC generation after interacting with the concerned RTL owner/owners. ● Partition execution starting from Floorplan till timing/layout DRC clean database for cutting edge wifi modem chipsets. ● Experience in last mile Timing/DRC convergence using Tweaker/Primetime in ECO Cycles. ● Convergence of large RTL change during ECO phase, Consumed large addition of Gate count during pre BTO stage. ● Have experience in Handling Timing ECO during BTO Stage. ● Responsible for low power Formal Equivalence/reliability verification (EM/IR) checks for owned partitions. ● Involved in Block and SOC layout DRC/ERC/PERC/LVS cleanup till signoff using ICV/Mentor Calibre.