Testimonials
Services
Video meeting . 20 mins
4.9
Basic Q & A in VLSI
Bridge gap b/w college-level theory and real-world VLSI work
Video meeting . 30 mins
5
VLSI Resume Review
Polish your resume for VLSI dream Job
Video meeting . 120 mins
Priority DM . 2 days reply
5
Instant Guidance – VLSI Verification Mentorship
Get quick, priority mentorship on VLSI Design Verification
Video meeting . 80 mins
4.7
1:1 VLSI Mock Interview & Feedback Session
Full Mock (Complete interview + deep feedback)
Video meeting . 60 mins
5
From Student to VLSI Pro: How to Get Started
A beginner's guide to entering the VLSI industry
About me
Never Stop having Fun & Learning
Change the Perspective 🤸
Area of Expertise
• UVM, System Verilog, Verilog, Basics of PERL & Python
• Protocols - AMBA (AXI-4, APB), SPI, UART, I2C
• Develop Test Plan & Test Bench for Verification
• Low Power Verification & UPF quality verification fixes.
• Formal Verification
• Well Versed Knowledge in Computer Architecture
• Excellent debug skills with ability to quickly and accurately root cause failures and make high quality verification fixes.
Hands-on Experience
• SOC Verification
• IP/Sub-System Verification
• Performance Verification
• System Verilog Assertion implementation
• Worked on GATE LEVEL SIMULATION (GLS) - Zero Delay & SDF
• Constraint Random and self-checking verification environment
• Worked on Low Power Verification & UPF
• Developed C-based test case
• Worked on Hardware/ Software Co verification
• Worked on FreeRTOS for HW/SW verification
• Worked on Python script development for automating runs and for debug analysis.