A highly organized and goal-oriented graduate student majoring in Electrical Engineering at University of Texas at Dallas. KNOWLEDGEABLE AND EXPERIENCE IN: •Logic Design, Logic Optimization, Synthesis, Validation, RTL Coding, Floor planning, Placement and Routing, Clock Tree Synthesis, Low Power Design Techniques, Static Timing Analysis, Verification,Linting,Testing, Scan Insertion, Debugging, Simulation. AREAS OF EXPERTISE INCLUDE: •Hardware Descriptive Language: Verilog,System Verilog •Programming Languages: C,C++,SQL •Scripting Language: Python, TCL •Cadence Tools: Virtuoso Schematic/Layout Editor,Encounter,Spectre •Synopsys Tools: PrimeTime, Design Vision,HSPICE,Waveview,Liberty NCX,TetraMax •Operating System: Linux,Unix STRENGTHS: •Proficient in Communication •Skilled at solving complex problems. •Strong Leadership qualities; able to prioritize, delegate tasks and make sound decisions quickly.