I am a Software EDA Engineer at Intel Corporation, with over six years of experience in developing solutions to automate chip layout generation using pcells and SKILL code in Cadence Virtuoso and Custom Compiler. I am passionate about creating innovative and efficient software modules that enable faster and better design of analog and digital devices for the next generation of Intel technologies. As a core developer for the Analog Device Template library, I use my expertise in PDK development, Python programming, and software development life cycle to create and validate various PDK components, as well as to develop tools for QA automation. I also own the tech meeting agenda and track the health of the Pcell/PyCell tickets for the Advanced Design Group. Previously, as a VLSI CAD Engineer, I worked as a program manager and technical lead for the 10nm TestChip project, where I improved team efficiency by planning, tracking, and ensuring visibility of execution of templates and Linux environment support. I am always eager to learn new skills and technologies, and to collaborate with other engineers and experts to deliver high-quality and cutting-edge solutions.