PD Engineer with 2+ years of experience and with demonstrated history of working on complex designs from Synthesis to Route. I have worked on ARM-Based soc (cortex -x2) from Synthesis to Route (RTL to GDS). Created the optimal Floorplan for CPU block , Created Power-Plan based on TSMC N5 Specs and improved the flow for Timing and DRCs. Implemented a comprehensive power plan script for the block level design, which includes creating power rails, power stripes, via pillars, and connecting macros to the power stripes. Experience in Floor Planning ,Power Planning ,Hierarchical Flow ,STA, Placement to Route on N5 an N7 Tech Nodes. Have basic knowledge about UPF ,Tech Files and DFT (Tessent). Proficiency in Calibre to execute nmDRC, nmLVS, and PERC checks, TCL scripting and Linux command line utility such as grep, sed, and awk to automate design flows.