Senior Digital Design Engineer at Renesas Electronics with 3+ yrs of experience in following domains: Micro architecture design of DSP blocks based on provided reference model in Python for bit accurate modelling, Safety Mechanisms like Temperature Sensor, Voltage Monitoring , Power Monitoring based on thresholds, Digital parts of PLL block, Clock Generation block for complete IC for different functionality . Detection of Interference in incoming data to the Radar followed by Mitigation mechanism and storage of Interference information to be read for further processing. RTL Design from scratch for all the above mentioned blocks . Generation of testcases based on already available Verification Environment for Bit Accurate Matching of RTL and Python Outputs for above blocks. Lint and CDC Checks on the RTL Creating GLS Flow and running GLS Simulation for owned blocks Creating VCD file based on GLS Simulation for IR drop calculation SDC constraints Update for newly added blocks and performing Synthesis to debug any failing Setup for Hold Paths. Code Coverage Closure for the owned RTL Design blocks by adding new testcases if required Functional ECO on Synthesized Intermediate and Final Netlist followed by LEC On Chip debug through C++ API testcases for the owned blocks Performing STA Checks based on timing reports given by PD Team Validation of IC for complete datapath functions. Tools Used - Simvision, Jaspergold, Genus, IMC, Conformal Languages Used - System Verilog, Verilog, Shell, UVM , Python