Currently working with Qualcomm as a Senior DFT Engineer. Prior to this I worked at Tenstorrent with the DFT and Test Team as a DFT intern for 6 months, my work involved creating architecture and microarchitecture for AI chiplets. Prior to this I interned at Intel, IFS in the DFT team, a position I held for six months. My responsibilities included migrating Design Complier scripts to Fusion Compiler, ensuring functional equivalence and enabling the team to use industry-standard tools. Using Spyglass DFT connectivity checks were performed on MBIST-inserted RTL (Scan insertion was performed using FC tool). Worked on inserting DFT Features like wrapper (using internal pin flow) into a taped-out design. Automated the generation of SGDC file used for Spyglass DFT using Python These internships were concurrent with my Master's program at Portland State University, where I specialized in Electrical and Computer Engineering. Before I pursued masters, I accumulated around four years of experience as a Design for Testability Application Engineer II at Synopsys. I worked with various Synopsys Tools under the TestMAX suite while focusing on scan insertion, analysis at the ATPG, DFT DRC, low coverage analysis, and Simulation. I applied my expertise to support customers in implementing and verifying DFT solutions for their chips. I have hands-on experience using TestMAX tools to perform synthesis, test pattern generation, and timing analysis for technologies ranging from 40nm to 7nm.