► Working as DFT Engineer in SoC Core-based DFT bubble ► Hands on experience on robust SSN based scan insertion and DFT stitch ► Familiar with Tessent SSN architecture, EDT, ATPG, fault models, scan tracing and DRC analysis ► RTL and Gate level integration for DFT hardware ► Execution of Spyglass DFT DRC for DFT connectivity checks ► Proficient in Tessent, Mentor TK, TetraMax, Spyglass DFT, Synopsys verdi, Fusion Compiler and Design Compiler ► Proficient in Verilog, Python, TCL, shell scripting ► Gate level ECO implementation Highly adaptable and enthusiastic to new technologies/domains