Shivam is a skilled professional with 2.7 years of experience in design verification. His expertise lies in areas such as Verilog, system verification, and Universal Verification Methodology (UVM). He possesses extensive knowledge of protocols including AXI, APB, Ethernet and JTAG, enabling him to effectively verify complex designs and ensure their functionality. With hands-on experience in Register Abstraction Layer (RAL), Shivam is adept at creating and managing register models, facilitating efficient verification of register-based designs. His strong understanding of verification methodologies and industry-standard practices allows him to develop robust testbenches and verify designs with accuracy and thoroughness.