Hi, I’m Sesham Abraham , a Passionate CPU Phy design and STA engineer with 7 years of professional experience in the VLSI industry. i have total 11+ years experience Currently, I’m Researching on confidential EDA tool-based projects. Setting up the CAD flow and writing the TCL Scripting. I bring a strong educational foundation to complement my practical experiences by having a master's degree MTech in VLSI SYSTEM DESIGN from JNTU Hyderabad and a Graduate Degree B.Tech in Electronics and communication from JNTU Ananthapur. In addition to this degree, I was trained in VLSI Design course in Central institute of tool design from Hyderabad and VLSI physical design from VLSI Guru at Bangalore. Have a good knowledge of physical design, STA and VLSI related topics. During this entire journey, I have specialized in the below mentioned following areas of work while handling the complex designs, debugging and providing solutions to the relevant issues and Design challenges, achieving better PPA and contributed to the 5 successful project tape outs from Netlist to GDSII at block level for various technology nodes ranging from 28nm, 14nm, 7nm, 5nm and 4nm. • Synthesis and Block level PNR (Floorplan, Power plan, Placement, CTS, Routing): • Signoff checks activities that include: • Physical verification (DRC, LVS, antenna). • Logical equivalence checks. • For timing closure (post layout static timing analysis checks, ECO’s, fixes of DRV, max capacitance, Crosstalk, min pulse width violations. Etc.). • Proficient in TCL scripting and hardware programming languages VHDL & Verilog. • Timing closure, RTL design, implementation of the same with different nodes of technologies • Successfully implemented and Timing closure. • Tools Used Summary: I have an extensive work experience with both the Cadence and Synopsys EDA tools. I have effectively utilized Synopsys tools in my latest project such as ICC2 - for PNR, PTSI - for STA, ICV, Caliber, for Physical verification.