6+ years of experience in semiconductor design, specializing in ESD compliance, LPE, EMIR ,PDN ,physical verification, and SOC/IP-level reliability. -> Good Experience in automating design flows and developing custom design tools using TCL, Perl, SKILL, and other programming languages. -> Hands-on experience with ESD tools and LPE extraction flow development using Mentor Calibre, Cadence Virtuoso, Quantus, voltus, totem and Redhawk. -> Worked on advanced process nodes from 180nm to 3nm, with strong knowledge of Finfet and 3DIC technologies. -> Good Knowledge in ESD HBM/CDM protection, current density checks, and design robustness methodologies. -> Previous role at Intel Corporation focused on memory layout design, EM/IR improvements, and signal optimization. -> Highly collaborative, with strong team bonding skills, delivering results across different cross-functional teams and global product lines. -> loves playing badminton and travelling.