DFT Engineering Lead with close to 15 years of diverse expertise on SoC DFT uArchitecture, DFT RTL Integration for EDT, SSN, OCC,IJTAG and IO loopback, Power aware DFT Implementation, ATPG, SoC DFT Verification, Power Aware GLS, Si - debug, FI FA( LADA, LVI/LVP ) , yield fallout debug and ramp. Extensive knowhow and hands on experience on UPF strategy definitions for test, CLP, power aware test concepts and methodologies, Low power systems, verification and validation. Led full spectrum of DFT functions for multiple SoCs starting from architecture to Si and beyond with a blend of unconventional and effective leadership and management skills. Led CPU and Modem subsystem Scan implementation, ATPG, hard macro level CLP signoff for test crossings, subsystem level test mode constraints management and Test Timing closure as part of Qualcomm's core DFT team. Pioneered power aware simulation flow bringup and deployment of advanced features for retention test scenarios across projects within the DFT org. High level of expertise in SoC Scan and MBIST unit delay, timing & power aware simulation debugs. RTL X-bounding for LBIST, LBIST IP integration (clk and rst controllers ). SpyGlass RTL DFTDRC checks for clock connectivity, memory control pin connectivity, async set/reset connectivity, DFTDSM at speed clocking checks. Synthesis, Test mode STA, Test Clocking, FV, PTPX Power Analysis. CPU power aware DFT implementation and different facets of static verification including DFD features like jtag and apb scan dump, memory dump.Memory BIST & redundancy architecture, Insertion, verification using fault injection, Test vector development and Si - debug. DFT signoff reviewer for tape out and Silicon bring up and debug for volume production. Dealt with customer RMAs at times and involved into collaborative debugs with functional & system DV for root-cause. Highly people oriented technical manager with experience line managing medium to big sized teams.