Initially started as SoC Design Engineer in RTL integration starting right away after IP delivery from Checks along with memory integration. End to End IP integration to SoC meeting all the connectivity aspects , Static checks (CDC , Lint , VCLP ) etc Currently i work on the generation and integration of an In-house IP associated with NOC used for protocol conversion ( from IP to NOC). Integration involves the connectivity , static checks quality , vclp issues resolution etc. I started as an intern in the Physical design mainly focused on Signoff checks in block level as well as ss level related to quality, connectivity , timing etc. During my academic years, I have studied on various topics which includes Digital VLSI design, Low Power design, Digital design through verilog etc.