7+ Years of hands on Experience in Deep sub-micron Process Technologies(7nm, 5nm, 14nm, 18nm, 22nm, 28nm) in TSMC, Samsung and Intel. Worked on Layout for GPIO Cells, USB2, C2C, HSIO and Multi-protocol SERDES IPS. Worked on Layout for various critical Blocks like LDO, BGR, CTLE, Rx, Tx, Clocking Blocks and Resistor Calibration Blocks. Very Good at Understanding the Layout Multi-Stack Methodology and working on Migrating from one to other and vice-versa.