• 4+ years working experience as a Lab Engineer under SMDP-C2SD project has been initiated by Ministry Of Electronics & Information Technology(MeitY), Govt. of India . • Work experience with the project team and Institute collaboration at SGSITS, Indore. • Research experience in Biomedical signal monitoring analog front-end design in CMOS technology(SCL library kit) with sub-blocks Instrumentation amplifier, Filter, etc. • Worked as a faculty in Electronics and Communication department, Engineering College Ujjain for 3 years. • Expertise in VLSI circuit schematic and layout design. • Experience and Knowledge in installation and use of VLSI EDA tools like Cadence, Mentor Graphics, Synopsys for front-end and back-end design. • Experience in Xilinx FPGA design cycle and worked on Spartan-3E, Nexys 4 DDR, Basys 3, Zynq-7000 SoC, and Analog Discovery Kit. • Well understanding of layout design, verification, simulation with DRC, LVS, Extraction. Technical Experience: • Domain: ASIC/FPGA design & verification, Circuit schematic, and layout design. • Software tools: Cadence(Virtuoso Schematic and Layout editor, Spectre Simulator, Analog Design Environment, Genus Synthesis Solution, Innovus Implementation system custom IC design tool), Mentor Graphics(Pyxis Schematic and Layout Editor, Eldo Simulator, EZwave, Calibre, Precision Synthesizer, Leonardo Spectrum, Questasim, Modelsim), Synopsys, Xilinx, Vivado, Sonnet, Advanced design system(ADS), eclipse. • Operating system: Windows, Linux/Unix. • Languages: VHDL, Verilog.