ASIC Style RTL design Bootcamp with Rohan Peter

RTL-to-Synthesis Bootcamp

Master the complete Front-End ASIC Design Flow using Xilinx Vivado through production-grade, 100% hands-on module and subsystem design.

Course Overview

*ASIC style RTL Design & Integration: Write and integrate clean, Verilog code for standard protocols.

* Lint Analysis: Set up automated rules to eliminate latches, feedback loops, and non-synthesizable code smells.

* CDC Analysis: Design and analyze robust synchronization circuits (Async FIFOs, Handshakes) to eliminate metastability.

* SDC Constraints: Write comprehensive Synopsys Design Constraints from scratch, including clock setups and timing exceptions.

* Logic Synthesis: Run Vivado synthesis engines to map RTL to hardware blocks while optimizing for area, power, and speed.

* Post-Synth STA: Deep-dive into timing reports to identify and fix setup violations through pipelining and optimization.

* Post-Synth Simulation: Execute gate-level simulations (GLS) using netlists and SDF files to catch functionality mismatches.