Over 13 years of semiconductors experience. Expertise in Memory compiler Layout and Tiler/Netlister development. Worked on technology nodes from 90nm to 5nm. Hands on experience with Bulk CMOS, SOI CMOS, FINFET. Expertise in DRC, LVS, ERC, EMIR, DFM, Antenna, Lacthup, Litho. Good debugging and automation skills. Sound knowledge on CMOS device physics. Highly motivated and enthusiastic contributor in the team. Guided 100s of graduates and post graduates into VLSI career • Two port Register File –5nm FINFET • Dual port High Speed SRAM –7nm FINFET • Single port High Density SRAM –7nm FINFET • Analog Layouts (Opmamp, BGR, Resistors, Capacitors) –7nm FINFET • TEST CHIP (Dual port Register File, Single port High Density, Single port High Performance, CAM) – 7nm FINFET • Dual port High Performance SRAM –10nm FINFET • Dual port High Performance SRAM –16nm FINFET • Single port High Density, Performance SRAM –16nm FINFET • Pseudo Dual Port SRAM: 14nm FINFET • Pseudo Dual Port SRAM: 22nm SOI • Single Port Register File: 32nm SOI • I/O Layouts & Characterization – 45nm, 60nm, 90nm