Having vast exposure to RTL & hardware design. Work Summary -> Experience with RTL coding using HDL language(s) - VHDL / Verilog / System Verilog. -> Experience in test bench based RTL simulation, debug and code coverage analysis. -> Experience in FSM design, micro-controller based sub-system design, digital interface IPs . -> Experience in Clock domain crossing/Timing analysis. CDC, Linting -> Good understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floorplanning, ECO, bring-up & lab debug