I'm an experienced RTL Design Engineer with over 6 years of hands-on expertise in digital design. My core strengths lie in microarchitecture design, Verilog/SystemVerilog coding, timing analysis, and logic synthesis. I've successfully developed and integrated IPs such as SPI, APB, AHB, and MIPI-UniPro, and have a strong command of LINT, CDC, and synthesis flows. I have knowledge of ATPG, which adds to my capability in ensuring design testability and quality. In recent years, I’ve focused on automotive and safety-critical applications, contributing to PCIe Gen5 and Gen6 developments with a solid understanding of ISO26262 and Functional Safety (FuSa) standards. I enjoy working on complex SoC designs and collaborating across teams to deliver high-quality, reliable IPs.