I am a final-year Electronics and Communication Engineering student at MNIT Jaipur, currently specializing in the VLSI domain with a strong focus on Physical Design. I am currently undergoing advanced training at Maven Silicon, where I’m gaining hands-on experience in the complete backend flow, including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. I have also worked with SDC constraints, static timing analysis (STA), IR drop analysis, power planning, and DRC/LVS checks. These tool-based labs and industry-oriented projects have strengthened my understanding of delay optimization, congestion handling, and sign-off processes for deep submicron technologies. Alongside VLSI, I’ve also explored AI/ML applications in biomedical signal processing. In a recent research project, I achieved 98.52% accuracy in detecting epilepsy from EEG signals using Convolutional Neural Networks (CNNs), showcasing my ability to bridge hardware knowledge with modern AI techniques. I am actively seeking a full-time opportunity starting July 2025 in the semiconductor industry, particularly in Physical Design. I’m passionate about solving real-world backend challenges and contributing to high-performance, silicon-proven SoC implementations.