DOMAIN :- Front-End Design and Verification(VLSI). SKILLS :- Verilog | System Verilog | UVM | C language | Linux CORE SKILLS :- Advance Digital Electronics Design TOOLS :-Vivado Projects :- # Mini Project: Developed a digital name board for institutional use. # Major Project: Successfully implemented FPGA-to-FPGA communication with a real-time serial data interface. Extra-Curricular Activities :- # Organized various events as a member of ECE Dept club, Team Clique # Volunteered in multiple organizations Achievements :- Winner in District Level Carrom Competition