ASIC Design Verification Engineer with 7+ years of experience, specializing in pre-silicon verification, hybrid simulation-emulation workflows, and PCIe/CXL/DDR5 protocol validation. Proven track record of first-test bring-up on GPUs and SoCs, delivering verification acceleration through reusable UVM infrastructure, debug automation, and performance-focused validation. Adept in cross-functional collaboration and technical leadership across global silicon projects.