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Video meeting . 30 mins
Entry in vlsi industry in frontend for fresher.
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About me
"Precision-driven Design Verification Engineer 🛡️ | Fluent in SystemVerilog,UVM,Linux,Gvim,scripting and Verilog 💻 | Unraveling Complex Designs for Reliability 🔍 | Enthusiastic in formal methods, upf & functional verification.🚀 #DesignVerification #DigitalEngineering"
- RahuLMoglI (Rahul Kumar Singh) · GitHubhttps://github.com/RahuLMoglI
