• MemoryBIST insertion, validation and Debug • EDT & OCC insertion • Built tessent stand alone dofiles for MemoryBIST & ATPG • ATPG for both stuck-at & at-speed fault models • DRC fix • Coverage Improvement • Scan & wrapper cell insertion • No-timing & timing simulations • Good understanding of JTAG, IJTAG. (SIB's & TDR's)