💪 Strengths Foundation in RTL Design, Synthesis, and Physical Design Flows, honed over a year of industry experience. Proficient in timing closure, power optimization, and physical verification (DRC/LVS) for complex designs. Quick learner with a proven ability to adapt to new tools and technologies in the dynamic VLSI domain, particularly in full-chip design. Effective communicator and proactive team player, with a results-driven mindset. 🎯 Core Competencies Design and Implementation: End-to-end ASIC design, including RTL to GDSII flow and clock tree synthesis. Tools Expertise: Hands-on experience with Mentor Graphics tools for backend implementation. Analysis and Debugging: Skilled in static timing analysis, IR drop, and electromigration analysis. Collaboration: Strong cross-functional teamwork, client interaction skills, and leadership in handling key customer engagements. 🌟 Professional Achievements and Projects Played a key role in creating a comprehensive document on shrinking die area, aiding in design optimization. Enhanced report content generated after each PnR stage, improving clarity and usability using AI models. Successfully identified and resolved challenges related to power net DRC, ensuring design integrity. Optimized a block on an N5 node, reducing congestion and improving timing performance. 🔍 Personal Projects Designed and verified a simplified RISC-V processor core as a learning project. Automated repetitive design checks with a Python-based script, enhancing workflow efficiency. 💡 Targeting Opportunities Aspiring to advance as a Physical Design Engineer, focusing on timing analysis, backend implementation, and full-chip design. Passionate about contributing to cutting-edge semiconductor projects, whether in startups or established technology companies. 🎓 Certifications Certified in Physical Design Using Mentor Graphics Tools, foundational training in Timing Analysis, ASIC Bootcamp for VLSI Engineers: STA Basic Concepts, Digital Timing Basics for VLSI Interview & SoC Design, Verilog HDL: VLSI Hardware Design Comprehensive Masterclass, Digital Electronics, Verilog - Hardware Modeling. 🏆 Achievements Technical Excellence Award: Recognized as a Top Contributor for outstanding efforts and quality-driven contributions during a successful tapeout. Commended by the Business Technical Director for exceptional work in summarizing a complex engagement, demonstrating analytical and organizational acumen.