I am an experienced Design Verification Engineer with a strong background in VLSI. My skills include expertise in Universal Verification Methodology (UVM), System Verilog, Verilog, and Linux. I have a demonstrated history of delivering high-quality results and working collaboratively with cross-functional teams. As a Grade 10 professional, I bring a deep understanding of ASIC design principles and a passion for developing efficient and effective verification strategies. My strong Quality Assurance knowledge in ASIC enables me to identify and address issues in a timely manner, resulting in optimized product quality and performance. I am excited to leverage my skills and experience in a dynamic work environment where I can continue to learn and grow professionally.