As a Senior Design Verification Engineer at AMD, I work on verifying chips IPs/Sub-System/SoCs using SystemVerilog, UVM, and Agentic AI framework. My day-to-day involves building verification environments from scratch, writing test cases and assertions, closing functional/code coverage, and working closely with RTL designers to debug and root-cause issues before tapeout. I've worked across PCIe Gen1 - Gen6, AXI, AHB, I2C, SPI] and have hands-on experience taking blocks from test plan to coverage closure. Beyond the day job, I'm genuinely invested in helping people break into this field — I remember how confusing it was to figure out "VLSI" as a career path with almost no structured guidance available, and I want to be the mentor I wish I'd had. Technical Skills & Specialties: 👉 Languages: Verilog, SystemVerilog, C++, Python 👉 Verification Methodology: UVM 👉 Protocols: PCIe Protocol (Gen 1-Gen 6), High Speed SerDes 👉 EDA Tools: Cadence Simvision / Synopsys VCS / Questa Sim etc. 👉 Strong fundamentals in digital design and ASIC verification flow 👉 Test plan & testbench architecture development 👉 Assertion development, functional coverage, and coverage closure 👉 Block-level / chip-level / sub-system-level/ SoC level verification experience 👉 Worked closely with RTL teams on constrained-random and directed test cases for coverage-driven closure 🔧 Why Connect with Me? Been through it myself: I went through the same confusion, interviews, and rejections you might be facing now — and I know what actually works versus what's just noise. 1:1, no-fluff guidance: Book a session for honest advice on breaking into VLSI/DV, mock interviews, resume fixes, LinkedIn optimization, or hands-on project help — whatever stage you're at. For freshers and professionals alike: Whether you're trying to land your first role or move up from where you are, I'll tailor the conversation to where you actually are, not a generic script. 🚀 Let's figure out your path into VLSI — together. Book a session and let's get started!