I am a DFT engineer by training; my expertise also includes SCAN insertion, JTAG, and ATPG, among other DFT techniques. I had earned a Ph.D. Possess six years of research experience in the design and simulation of transimpedance amplifier with layouts using various technology nodes, including 45nm, 65nm, 90nm, and 180nm with Cadence tool. Possess three years of experience as an asst. professor. My publications include two chapters that are indexed by Scopus together with two SCIE paper and one ESCI paper Qualified GATE with 90.4 percentile