Design Verification Project: Build a Protocol VIP

It will be total 4 session (1 session per weekend). Valid for only 4 weeks from the date of start.

Pre-requisites : You should know basics of system verilog and UVM.

Course Description:

This hands-on course is designed to equip you with the practical skills and knowledge needed to excel in design verification. You'll gain experience in developing a complete verification environment (VIP) for a given design, a valuable asset for your resume and future career opportunities.

What You’ll Learn:

• Protocol Understanding: Learn to thoroughly analyze and comprehend the specifications of a chosen protocol.
• Test Plan Development: Master the creation of comprehensive functional test plans to guide the verification process.
• Testbench Development: Build a complete testbench for the protocol using SystemVerilog and the Universal Verification Methodology (UVM).
• Practical Application: Apply your knowledge to verify a provided design, gaining real-world experience.

Course Structure:

1. Protocol Deep Dive: In-depth exploration of the chosen protocol's architecture, features, and functionalities.
2. Test Plan Creation: Step-by-step guidance on developing a robust functional test plan, covering various scenarios and edge cases.
3. UVM Testbench Implementation: Hands-on development of a UVM-based testbench, including components like drivers, monitors, and scoreboards.
4. Design Verification: Applying the developed testbench to verify a given design, identifying and debugging potential issues.

Benefits of this Program:

• Gain practical experience in design verification, a highly sought-after skill in the semiconductor industry.
• Develop a project that you can showcase in your resume to demonstrate your expertise.
• Learn from an experienced Design Verification Engineer at Google.
• Enhance your understanding of UVM and SystemVerilog.