Explore, Experiment and be a Trendsetter! Currently working as SoC Design Engineer at Intel. Experience in working with different stages of Physical Design Implementation i.e Floor planning, Placement, Clock Tree Synthesis, Routing, ECO implementation for timing and functional fixes, Physical Verification , EM & IR fixes. Not just a believer, an innovator and an achiever!!! I possess good knowledge in the following- • Physical design implementation of SoC's , Floorplanning, Placement and Routing of complex SoC's • Low power Techniques , Conformal low power checks , Sign-off • Formal Equivalence Verification • Logical Equivalence checks • Reliability Verification ( IR Analysis , EM Analysis, Self Heat Analysis ) • Hardware Description Language : Verilog HDL • Scripting languages : PERL and TCL • EDA tools: Apache RedHawk , Synopsys ICC/ICC2 , Design Compiler , Conformal Low Power , VCLP ,Spyglass.