I am keen to contribute to the success and growth of the organization by undertaking challenging assignments and delivering timely results by applying the best of my knowledge and skills. --------------------------------------------------------------------- 🟡Working Domain:-Design and verification Engineering(IP verification, SOC Verification, Gate Level Simulation & functional verification). Worked with Scratch level Testbench /UVC Development, Tasks including BFM/VIP integration, Creating Test cases & Sequences as per the Test plan, Worked on Scoreboard development & integration. functional, Code Coverage, and Regression(have Worked on both NB flow & ITF flow). --------------------------------------------------------------------- 🟡Engineering/Domain Skills✅✅:-Uvm, System Verilog, Verilog, Digital circuit design, Perl scripting, Linux, ITF Scripting --------------------------------------------------------------------- Protocols:- AMBA AHB, APB, AXI4 lite, AXI streaming, Avalon streaming(AVST), Avalon memory mapped (AVMM), I2S, Automobile Peripheral Protocol: FLEX-RAY --------------------------------------------------------------------- 🟡Tools:-Synopsys VCS, VNC, Synopsys DVE(Graphical Interface for debugging & reviewing waveforms), Xtreme, Cheetah Flow, Git & Perforce. --------------------------------------------------------------------- 🟡OS:-Windows, Linux, Mac --------------------------------------------------------------------- 🟡 Others:-Microsoft Word, Excel, PowerPoint. ---------------------------------------------------------------------